A lateral diffusion metal-oxide-semiconductor field effect transistor (LDMOSFET) is a field effect transistor having a drift region between a gate and a drain region in order to avoid a high electric field at a drain junction, i.e., at the p-n junction between a body and the drain region. An LDMOSFET is typically employed in high voltage power applications involving voltages in the range from about 5 V to about 500 V, which is applied across the drain region and the source region. A substantial fraction of the high voltage may be consumed within the drift region in the LDMOSFET so that the electric field generated across the gate dielectric does not cause breakdown of the gate dielectric.
Referring to FIG. 1, a prior art LDMOSFET structure is shown, which comprises a body 31 having a doping of a first conductivity type and laterally abutting a drift region 41 having a doping of a second conductivity type, which is the opposite of the first conductivity type. The portions of the body 31 and the drift region 41 near the interface between them are herein referred to proximal ends since they are in proximity to the interface. The portions on the opposite ends are herein referred to distal ends. A source region 51 and the drain region 61, each having a heavy doping of the second conductivity type, are formed at a distal end of the body 31, and at a distal end of the drift region 41, respectively. A gate dielectric 71 and a gate electrode 81 are formed straddling the body 31 and the drift region 41 directly above the proximal ends of the body 31 and the drift region 41. A sufficient physical distance is provided for carrier diffusion between the interface and the drain region 61 for attenuating the electric field within the drift region either by providing shallow trench isolation 20 directly above the drift region 41 or by providing a sufficient length for the drift region 41 without forming shallow trench isolation thereabove. In case the shallow trench isolation 20 is employed above the drift region 41, the length of carrier diffusion across the drift region 41 is at least equal to the sum of the depth of the shallow trench isolation 20 directly above the drift region 41, the lateral width of the shallow trench isolation 20 directly above the drift region 41, and the difference between the depth of the shallow trench isolation 20 directly above the drift region 41 and the depth of the drain region 61. As such, in the case that shallow trench isolation 20 is present, the lateral distance between the body region 31 and the drain region 61 can be reduced, while achieving the same effective length of the drift region 41 compared to the case without a shallow trench isolation 20. Thus, the presence of shallow trench isolation 20 allows for a reduction in the area consumed by the transistor compared to the case without a shallow trench isolation 20. The drift region 41 is not directly externally biased. Four terminals, i.e., the body region 31, the source region 51, the drain region 61, and the gate electrode 81, are biased in the prior art LDMOSFET structure during operation. Oftentimes, the substrate region 10 has the same conductivity type doping as, and may be biased at the same voltage as, the body region 31. Generally, the tub region 11 has the same conductivity type doping, and is electrically connected to, the drain region 61.
Referring to FIG. 2, another prior art LDMOSFET structure disclosed by A. W. Ludikhuize, “High-Voltage DMOS and PMOS in Analog IC's,” IEDM 1982, pp. 81-84, comprises a gate dielectric 72 having multiple thicknesses. The body 32, which has a doping of a first conductivity type, laterally abuts the drift region 42, which has a doping of the second conductivity type, at an interface directly below the gate dielectric 72. The gate dielectric 72 has stepwise increases in thickness in the direction from an edge of a gate electrode 82 over the body 32 toward an edge of the gate electrode 82 over the drift region 42. A source region 52 and a drain region 62 are formed in distal ends of the body 32 and the drift region 42, respectively. The stepwise increase in the thickness of the gate dielectric 72 reduces electric field across the gate dielectric 72 near the edge of the gate electrode 82 over the drift region 42. The reduction in the electric field is beneficial to the integrity of the gate dielectric 72, especially in an off-state when a high voltage is applied across the portion of the gate dielectric 72 directly below the edge of the gate electrode 82 and over the drift region 42.
The portion of the gate electrode 82 which is over the drift region 42 is generally referred to as a “field plate.” While this example depicts the field plate as a portion of the gate electrode 82, it is sometimes formed as a distinct region which can be biased independently, but is generally biased at the same potential as the gate or source. In the case that the LDMOSFET is an n-type device, in an off-state, the gate electrode 82 and the source 52 are generally at approximately the same potential as the body 32, while the drain 62 is at a higher potential. An electric field exists laterally across the drift region 42, with the highest potential at the distal end near the drain 62, and the lowest magnitude potential at the proximal end near the body 32. An electric field also exists across the junction between drift region 42 and body 32. The electric field between gate electrode 82 and the drift region 42 causes an increased depletion of majority carriers in the drift region 42 below the gate electrode 82. This serves to reduce the electric field near the surface at the interface between the drift region 42 and the body 32, thereby increasing the effective breakdown voltage of the junction. For this reason, this type of device is termed “reduced surface field metal-oxide-semiconductor field effect transistor,” or RESURF MOSFET.
In the present example, when the device is on, the gate electrode 82 is generally at a higher potential than the source 52 and the body 32, while the potential of the drain 62 is often at approximately the same potential as the source 52 and the body 32. In this case, the resulting electric field between the gate electrode 82 and the drift region 42 causes an accumulation of majority carriers in the drift region 42, thus reducing the effective resistance of the drift region in the on-state, or “on-resistance.” As such, the addition of a field plate by extending the gate electrode over the drift region 42 provides a device which has an increased breakdown voltage between the body 32 and the drift region 42, yet has reduced on-resistance.
Typically, in order to minimize the electric field in the off-state of an LDMOSFET, the drift region is lightly doped and thus has a high resistance. However, the high resistance is undesirable in an on-state since the performance and efficiency is limited by the high resistance of the drift region. Reduction of on-resistance of the drift region generally comes at the expense of decreased breakdown voltage and device reliability, thus limiting the allowable operating voltage. Increase of resistance of the drift region results in an increase in the operating voltage at the expense of reduced performance and efficiency. One proposed solution involves the addition of a field plate over the drift region of the device. However, the prior art field plate is of limited usefulness in the case in which shallow trench isolation is employed. In such a case, the field plate would have to be positioned over the shallow trench isolation. However, the thickness of the shallow trench isolation would typically be too great to provide good capacitive coupling between the field plate and the underlying drift region, thereby limiting the effectiveness of the field plate to modulate carrier concentrations within the drift region. As such, the reduced LDMOSFET device area associated with the addition of shallow trench isolation cannot be realized with the prior art field plate.
Therefore, there exists a need for an LDMOSFET structure providing both a low on-resistance and a high operating voltage within a small device area, and methods of manufacturing the same.
Specifically, there exists a need for an LDMOSFET structure having a field plate to modulate the surface field and resistance of a drift region and shallow trench isolation to allow reduced device area, and methods of manufacturing the same.